Distributed feedback lasers formed via aspect ratio trapping

ABSTRACT

Structures including dielectric diffraction gratings. In some embodiments, laser devices include diffraction gratings defined by openings formed in a dielectric material.

RELATED APPLICATION

This application claims priority to U.S. Provisional Patent ApplicationSer. No. 60/852,781, filed Oct. 19, 2006, the disclosure of which ishereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

This invention relates generally to semiconductor processing andparticularly to formation of light-emitting devices based onlattice-mismatched semiconductor structures.

BACKGROUND

Distributed feedback (DFB) lasers with stable longitudinal single-modeoperation are critical for applications such as optical-informationprocessing, interferometric measuring, holographic printing, optical gassensing, atomic spectroscopy and medical diagnoses. Examples of variousDFB lasers are shown and described in U.S. Pat. Nos. 5,295,150 and5,953,361 and articles such as Japanese Journal of Applied Physics, Vol.43, No. 4B, 2004, pp. 2019-2022, Japanese Journal of Applied PhysicsVol. 44, No. 4B, 2005, pp. 2546-2548, and Journal of Crystal Growth 261(2004) 349-354, incorporated herein by reference in their entireties.

In order to obtain a longitudinal single-mode output, a buried gratingstructure design is widely used to introduce a periodic refractive indexchange in the active region of the laser, i.e., the portion of the laserin which light is propagated. This grating structure selectivelyreflects a certain Bragg wavelength in the laser gain spectrum. Byadjusting the grating pitch and the refractive index, single-mode lasingcan be realized. Currently, commercial 0.7-2.0 micrometer (μm) DFBlasers are mainly fabricated by employing MOCVD-based two-step growthmethods that have several technical challenges. Firstly, conventionalholography and chemical wet etching are generally used for gratingformation on GaAs or InP-based substrates or pre-growth layers. SinceDFB performance characteristics are sensitive to grating pitch width,depth, surface morphology and shape profile, it is a technical challengeto meet specific wavelength requirements without comprehensive processoptimization. Furthermore, epitaxial re-growth on a wafer surface havinga grating disposed thereon is a common procedure to complete full DFBstructure formation. It is well known that mass transport and gratedsurface oxidation (particularly for laser structures containing Al) aresignificant issues affecting device performance. Finally, conventionalDFB lasers in the wavelength range of 700 nanometer (nm)-2000 nm areprimarily fabricated using GaAs or InP as substrates. The costs of laserdevices fabricated from non-silicon (Si) wafers are high due to the highcost of the wafers and the inherent low processing yields of laserdevices.

SUMMARY OF THE INVENTION

Embodiments of the present invention include systems and methods forproviding DFB laser structures on lattice-mismatched semiconductorsubstrates, e.g., Si, by employing aspect ratio trapping (ART) growthmethods. The following benefits are provided by various embodiments.

Low-cost Si may be used as the substrate. Si-based device fabricationtechnology is more mature than that of III-V compound materials. Inaddition to significant wafer cost reduction, adapting large-wafer Siprocessing techniques for III-V laser device processing may enhance theDFB fabrication reliability and product yield, thus leading to betterdevice performance and further reduction of fabrication cost. Inaddition, a Si substrate has better thermal conductivity and a higherphysical hardness than conventional GaAs and InP materials. Using Si asa substrate therefore improves heat depletion control and devicepackaging.

Furthermore, it may be advantageous to use dielectric sidewalls definedby ART techniques for selective growth as well as for the grating media.In these embodiments, a dielectric mask has multiple functions. First,it enables trapping dislocation defects within a very thin transitionlayer. These defects are generated at an interface between differentmaterials, e.g., a III-V/Si interface, due to lattice mismatch andthermal-expansion differences between Si and III-V compounds. Byemploying an ART-based surface engineering process, device-quality lasermaterials may be grown on lattice-mismatched, e.g., Si, substrates.

Second, since interface defects are trapped toward a bottom portion ofthe trench, the grating profile may be formed in an upper portion ofepitaxial films, e.g., III-V materials, by utilizing a dielectric (e.g.,oxide) pattern as an optical grating media. Since the first or secondorder grating pitch width for commonly used DFB lasers is on a submicronscale, ART masks have a good dimensional match to the grating pitchrequirements for making DFB lasers.

Another benefit is that ART patterning can provide a large refractiveindex difference between the dielectric material, e.g., SiO₂ (1.46), andthe epitaxially grown material, e.g., GaAs (3.2). This refractive indexdifference is larger than the refractive index difference betweenconventionally used materials such as GaAs and AlGaAs, and leads to ahigh optical coupling constant. The simplified grating formationprocedure, which avoids a re-growth process, is another significantbenefit in comparison to conventional methods of forming DFB structures.

The use of well developed integrated circuit (IC) processes for formingthe grating pattern allows for flexibility in grating geometry becauseselection of grating duty cycle and the variation of grating pitches canbe realized in an initial photolithography process. This offersadvantages over conventional post-growth holographic techniques.

The approaches described herein for realizing III-V/Si integrationcoupled with integration with conventional Si-based process enable avariety of other benefits as well, such as accommodating chip-scaleintegration of DFB lasers with other electronic devices.

In an aspect, the invention features a method of making a laser diode.The method includes forming a dielectric layer over a top surface of thesubstrate including a first semiconductor material. A plurality ofopenings are defined in the dielectric layer, with the openingsextending to the top surface of the substrate. A second semiconductormaterial is formed in the openings. A plurality of layers are definedover the second semiconductor material and the dielectric layer to formthe laser diode, with portions of the dielectric layer defining adiffraction grating.

One or more of the following features may be included. The diffractiongrating may have a width and a spacing selected to provide a duty cycleranging from 20% to 50%. Defining the plurality of openings may includereactive ion etching. Forming the second semiconductor material mayinclude selective epitaxy. The first semiconductor material may includesilicon and the second semiconductor material may include a III-Vcompound and/or a II-VI compound. The plurality of semiconductor layersmay include a cladding layer, a grating layer, a graded spacer layer, agraded confining layer, a quantum well region, and/or a cap layer. Thelaser diode may be a distributed feedback laser diode.

A bottom contact layer may be defined over a bottom surface of thesubstrate. A bottom portion of the second semiconductor material mayinclude lattice-mismatch defects and a top portion of the secondsemiconductor material may be substantially free of lattice-mismatchdefects. Each of the openings may have a height sufficient for trappinga majority of the lattice-mismatch defects within the opening. Each ofthe plurality of openings may have a width less than or equal to aheight thereof.

In another aspect, the invention features a semiconductor device. Thesemiconductor device includes a plurality of openings defined in adielectric layer disposed above a crystalline substrate comprising afirst semiconductor material. A diffraction grating defined by portionsof the dielectric layer is disposed between the openings. A secondcrystalline material is disposed within each of the openings, the secondcrystalline material having a lattice mismatch with the substrate, and amajority of defects arising from lattice mismatch between the secondmaterial and the substrate exiting at a surface of the second materialwithin each of the openings. A plurality of semiconductor layers aredisposed above the second crystalline material and the diffractiongrating, the plurality of semiconductor layers forming a laser diode.

One or more of the following features may be included. The firstsemiconductor material may include or consist essentially of silicon.The second crystalline material may include a III-V compound and/or aII-VI compound. The diffraction grating may provide a duty cycle rangingfrom 20% to 50%. The laser diode may be a distributed feedback laser.

In another aspect, the invention features a distributed feedback laserdevice including a dielectric diffraction grating disposed over acrystalline substrate and a plurality of layers disposed above thediffraction grating. The layers define a laser diode, and at least someof the layers comprise a III-V material lattice-mismatched to thecrystalline substrate.

One or more of the following features may be included. The diffractiongrating may include a dielectric layer defining a plurality of openings.A crystalline material may be disposed within the openings, thecrystalline material having a lattice constant mismatched to a latticeconstant of the crystalline substrate. A contact may be disposed on abottom side of the crystalline substrate. An input electrode and anoutput electrode may be disposed on a single side of the crystallinesubstrate. A top portion of the crystalline material may besubstantially free of defects. The crystalline substrate may include agroup IV material.

In another aspect, the invention features a method of making a laserdiode. The method includes forming a dielectric layer over a crystallinesubstrate including a first semiconductor material. A first diffractiongrating is formed by defining a first plurality of openings in thedielectric layer above a top surface of the crystalline substrate, thefirst diffraction grating generating a first output wavelength. A seconddiffraction grating is formed by defining a second plurality of openingsin the dielectric layer above the top surface of the crystallinesubstrate, the second diffraction grating generating a second outputwavelength. A plurality of layers is defined over the first and seconddiffraction gratings to form the laser diode.

In yet another aspect, the invention features a distributed feedbacklaser device. The distributed feedback laser device includes adielectric layer disposed over a crystalline substrate including a firstsemiconductor material. A first diffraction grating is defined by afirst plurality of openings in the dielectric layer above a top surfaceof the crystalline substrate, the first diffraction grating generating afirst output wavelength. A second diffraction grating is defined by asecond plurality of openings in the dielectric layer above the topsurface of the crystalline substrate, the second diffraction gratinggenerating a second output wavelength. A plurality of layers disposedover the first and second diffraction gratings define a distributedfeedback laser device active region.

BRIEF DESCRIPTION OF FIGURES

In the drawings, like reference characters generally refer to the samefeatures throughout the different views. Also, the drawings are notnecessarily to scale, emphasis instead being placed upon illustratingthe aspects of the invention.

FIGS. 1-4 are schematic cross-sectional view illustrating structuresformed in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

Referring to FIG. 1, a method for forming a relatively low defect ordefect-free semiconductor material on a lattice-mismatched substrate isillustrated. A substrate 100 includes a first crystalline semiconductormaterial S1. The substrate 100 may be, for example, a bulk siliconwafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI)substrate, or a strained semiconductor-on-insulator (SSOI) substrate.The substrate 100 may include or consist essentially of the firstsemiconductor material S1, such as a group IV element, e.g., germaniumor silicon. In an embodiment, substrate 100 includes or consistsessentially of n-type (100) silicon. The substrate 100 may include amaterial having a first conductivity type, e.g., n⁺Si.

A dielectric layer 110 is formed over the semiconductor substrate 100.The dielectric layer 110 may include or consist essentially of adielectric material, such as silicon nitride or silicon dioxide. Thedielectric layer 110 may be formed by any suitable technique, e.g.,thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD).As discussed below, the dielectric layer may have a thickness t₁corresponding to a desired height h of crystalline material to bedeposited in an opening formed through the dielectric layer. In someembodiments, the thickness t₁ of the dielectric layer 110 may be in therange of, e.g., 25-1000 nm. In a preferred embodiment, the thickness t₁is 600 nm.

A mask (not shown), such as a photoresist mask, is formed over thesubstrate 100 and the dielectric layer 110. The mask is patterned toexpose at least a portion of the dielectric layer 110. The exposedportion of the dielectric layer 110 is removed by, e.g., reactive ionetching (RIE) to define an opening 120. Opening 120 may be defined by atleast one sidewall 130, and may extend to a top surface 135 of thesubstrate 100. The height h of the sidewall 130 corresponds to thethickness t₁ of the dielectric layer 110, and may be at least equal to apredetermined distance H from a top surface 135 of the substrate.

The opening may be substantially rectangular in terms of cross-sectionalprofile, a top view, or both, and have a width w that is smaller thanthe length l (not shown) of the opening. For example, the width w of theopening may be less than about 500 nm, e.g., about 10-500 nm, and thelength l of the opening may exceed each of w and H. The ratio of theheight h of the opening to the width w of the opening 120 may be ≧0.5,e.g., ≧1. The opening sidewall 130 is configured to allow defects thatarise within the material S2 to exit the material below the height h asdescribed below. The opening sidewall 130 is not necessarily strictlyvertical.

A second crystalline semiconductor material S2, i.e., crystallinematerial 140, is formed in the opening 120. The crystalline material 140may include or consist essentially of a group IV element or compound, aIII-V compound, or a II-VI compound. Examples of suitable group IVelements or compounds include germanium, silicon germanium, and siliconcarbide. Examples of suitable III-V compounds include galliumantimonide, gallium arsenide, gallium nitride, gallium phosphide,aluminum antimonide, aluminum arsenide, aluminum nitride, aluminumphosphide, indium antimonide, indium arsenide, indium nitride, indiumphosphide, and their ternary or quaternary compounds such as indiumgallium arsenide, indium gallium nitride, indium gallium phosphide, etc.Examples of suitable II-VI compounds include zinc selenide, zincsulfide, cadmium selenide, cadmium sulfide, and their ternary orquaternary compounds.

The crystalline material 140 may be formed by selective epitaxial growthin any suitable epitaxial deposition system, including, but not limitedto, metal-organic chemical vapor deposition (MOCVD),atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD(LPCVD), ultra-high-vacuum CVD (UHCVD), molecular beam epitaxy (MBE), oratomic layer deposition (ALD). In the CVD process, selective epitaxialgrowth typically includes introducing a source gas into the chamber. Thesource gas may include at least one precursor gas and a carrier gas,such as, for example, hydrogen. The reactor chamber may be heated by,for example, RF-heating. The growth temperature in the chamber may rangefrom about 300° C. to about 900° C., depending on the composition of thecrystalline material. The growth system may also utilize low-energyplasma to enhance the layer growth kinetics.

The epitaxial growth system may be a single-wafer or multiple-waferbatch reactor. Suitable CVD systems commonly used for volume epitaxy inmanufacturing applications include, for example, an Aixtron 2600multi-wafer system available from Aixtron, based in Aachen, Germany; anEPI CENTURA single-wafer multi-chamber systems available from AppliedMaterials of Santa Clara, Calif.; or an EPSILON single-wafer epitaxialreactor available from ASM International based in Bilthoven, TheNetherlands.

In an exemplary process, a two-step growth technique is used to formhigh-quality crystalline material 140, consisting essentially of GaAs,in the opening 120. First, the substrate 100 and dielectric layer 110are thermally annealed with hydrogen at approximately 800° C. forapproximately 15 minutes to desorb a thin volatile oxide from thatsubstrate surface 135 that may be produced during pre-epitaxy waferpreparation. Chamber pressure during annealing may be in the range ofapproximately 50-100 Torr, for example 75 Torr. After annealing, thechamber temperature is cooled down with hydrogen flow. In order tosuppress anti-phase boundaries (APDs) on substrate surface 135, apre-exposure to As for about 1 to 5 minutes is performed. This stephelps ensure uniform coverage of the opening surface with an As—Asmonolayer. This pre-exposure is achieved by flowing AsH₃ gas through thereactor at a temperature of approximately 460° C. Then, a galliumprecursor, e.g., triethylgallium (TEG) or trimethylgallium (TMG), isintroduced into the chamber together with AsH₃ gas at a lower growthtemperature, e.g., approximately 400° C. to 450° C. to promote theinitial GaAs nucleation process on the As pre-layer surface. A slowgrowth rate of about 2 to 4 nm per minute with V/III ratio of about 50may be used to obtain this initial GaAs buffer layer, with a thicknessof the GaAs buffer layer being selected from a range of about 20 to 100nm.

In one embodiment, a layer of n-type GaAs is grown above the bufferlayer at a constant growth temperature of approximately 680° C. and aV/III ratio of approximately 80 to obtain relatively defect-free GaAsmaterial inside the opening 120. The combined thickness t₂ of theinitial GaAs buffer layer and the n-type GaAs grown above the bufferlayer may be less than or greater than the dielectric mask thickness t₁.The top portion of the GaAs material may coalesce with GaAs formed inneighboring openings (not shown) to form an epitaxial layer. The widthw2 of the crystalline material 140 extending over a top surface 160 ofthe dielectric layer 110 may be greater than the width w of the opening120. The overall layer thickness t₂ of the crystalline material 140 maybe monitored by using pre-calibrated growth rates and in situ monitoringequipment, according to methods known in the art.

Dislocation defects 150 in the crystalline material 140 reach andterminate at the sidewalls of the opening 120 in the dielectric material110 at or below the predetermined distance H from the surface 135 of thesubstrate, such that dislocations in the crystalline material 140decrease in density with increasing distance from the bottom portion ofthe opening 120. Accordingly, the upper portion of the crystallinematerial has a substantially reduced number of dislocation defects.Various dislocation defects such as threading dislocations, stackingfaults, twin boundaries, or anti-phase boundaries may thus be generallyeliminated from the upper portion of the crystalline material.

The crystalline material 140 may be considered to have two portions: alower portion for trapping dislocation defects and an upper portionwhich either (a) incorporates the laser or LED epitaxial layers or (b)serves as a template for the subsequent epitaxial growth of the laser orLED epitaxial layers. The height h of the crystalline material thus hastwo components: the height h_(trapping) of the lower portion (wheredefects are concentrated) and the height h_(upper) of the upper portion(which is largely free of defects). The height h_(trapping) of thetrapping portion may be selected from a range of about½w≦h_(trapping)≦2w, to ensure effective trapping of dislocation defects.The actual value of h_(trapping) required may depend upon the type ofdislocation defects encountered, which may depend on the materials used,and also upon the orientation of the opening sidewalls. In someinstances, the height h_(trapping) can be greater than that required foreffective defect trapping, in order to ensure that the dislocationdefects are trapped at a sufficient distance away from the upperportion, so that deleterious effects of dislocation defects upon deviceperformance are not experienced. For example, h_(trapping) may be, e.g.,10-100 nm greater than required for effective trapping of defects. Forthe upper portion, the height h_(upper) may be selected from the rangeof approximately ½w≦h_(upper)≦10 w.

Referring to FIGS. 2 a and 2 b, in an exemplary embodiment, the processdescribed with respect to FIG. 1 is used to form a laser diode 200,e.g., a DFB laser diode that emits optical radiation at a wavelengthless than 880 nm. The laser diode 200 is formed over the crystallinematerial 140. The laser diode 200 includes a plurality of openings 120with dielectric layer 110 portions, i.e., ridges, disposed between theopenings 120. The dielectric layer 110 is patterned to define a seriesof ridges defining a grid layer that forms a diffraction grating 210 ofthe laser structure 200.

The laser diode 200 includes a number of layers that may be formed byepitaxial growth in any suitable epitaxial deposition system, including,but not limited to, MOCVD, APCVD, LPCVD, UHVCVD, MBE, or ALD.

More particularly, laser diode 200 comprises a substrate 100 thatincludes a semiconductor material of one conductivity type. Thedescribed embodiment has an n-type substrate, including n+ type Si. Oneof skill in the art will recognize that other embodiments are possibleincluding, e.g., other material compositions and conductivity types. Thesubstrate 100 has a top surface 220 and a bottom surface 230. Thediffraction grating 210 is defined by dielectric layer 110 portionsformed on the top substrate surface 220. The openings 120 of thediffraction grating 210 have a selected width and a spacing ratio (dutycycle) ranging from 20% to 50% and preferably from 35% to 40%. The dutycycle is a ratio of the width of a dielectric ridge to the gratingpitch, with the grating pitch Λ being equal to a sum of the openingwidth w and the spacing d between openings 120 (with spacing d beingequal to a width of a diffraction grating 210 ridge.) For example, thewidth w of each opening 120 may be 250 nm and a spacing d betweenopenings 120 may be 200 nm. The grating pitch Λ determines thewavelength λ of the laser diode 200, such that λ=²n_(e)Λ/m, where n_(e)is the effective refractive index of grating layer 270, and m is aninteger greater than zero (1, first order; 2, second order, . . . ).

To use the substrate as an electrical contact medium, the electricalconductivity (i.e., doping) type of the material initially formed on thesubstrate, e.g., the initial III-V materials on Si, should be the sameas that of the substrate. In one embodiment, crystalline material 140may include a low temperature buffer layer such as n-type GaAs depositedonto the exposed top Si surface 220. The GaAs buffer layer has athickness of about 15 nm to 30 nm with a preferred n-type doping levelof about 2×10¹⁸/cm³.

A first cladding layer 268 including n-type Al_(0.6)Ga_(0.4)As is grownon the crystalline material 140 at an elevated temperature to a dopinglevel of 0.2-2×10¹⁸/cm³, with a preferred thickness of between 0.2-0.8μm. The combined thickness of the crystalline material 140 and the firstcladding layer 268 disposed within the openings 120 is less than aheight of the grid layer.

A grating layer 270 is grown on the first cladding layer 268. Thegrating layer 270 may include n-type Al_(0.4)Ga_(0.6)As. The gratinglayer 270 is n-type doped at a doping level of between 2×10¹⁶/cm³ to5×10¹⁸/cm³ and preferably about 5×10¹⁷/cm³. The grating layer 270 has athickness of between about 20 and 500 nm, preferably about 120 nm. Sincethe grating layer 270 is partially grown inside the openings 120 andcontinuously grown after coalescence over the dielectric grids 110, thetop parts of the dielectric grids defined by dielectric layer 110portions are surrounded by the grating layer 270.

A graded spacer layer 272 is grown on the grating layer 270. The gradedspacer layer 272 includes AlGaAs, preferably Al_(0.6)Ga_(0.4)As at thesurface of grating layer and Al_(0.4)Ga_(0.6)As away from the gratinglayer 270. The spacer layer 272 is n-doped with a doping level ofbetween 2×10¹⁶/cm³ to 5×10¹⁸/cm³ and preferably about 5×10¹⁷/cm³. Thespacer layer 272 has a thickness selected from a range of between about20 and 500 nm, preferably about 100 nm.

A graded first confining layer 274, i.e., a first waveguide, of undopedAl_(0.60-0.20)Ga_(0.40-0.80)As is formed over the graded spacer layer272. The graded first confining layer 274 has a thickness selected froma range of between about 20 and 400 nm, preferably about 120 nm.

An active layer (also referred to herein as active region), including amulti-quantum well region 280 is formed over graded first confininglayer 274. Referring also to FIG. 3, the multi-quantum well region 280includes a first quantum well layer 276 of undoped GaAs having athickness of, e.g., about 3 to 7 nm. Disposed over the first quantumwell layer 276 is a barrier layer 275 of Al_(0.05-0.60)Ga_(0.40-0.95)As,preferably Al_(0.25)Ga_(0.75)As. The barrier layer 275 has a thicknessof between 5 and 100 nm, and preferably has a thickness of 40 nm. Asecond quantum well layer 278 of undoped GaAs is disposed over thebarrier layer 275. The second quantum well layer 278 has a thickness ofabout 3-7 nm.

A graded second confining layer 282, i.e., a second waveguide, ofundoped Al_(0.20-0.60)Ga_(0.80-0.40)As is formed over the second quantumwell layer 278. The graded second confining layer 282 has a thickness ofbetween about 20 and 400 nm and preferably 120 nm.

A second cladding layer 284 is formed over the graded second confininglayer 282. The second cladding layer 284 is graded p-type, and includesAl_(0.4-0.6)Ga_(0.6-0.4)As as the second confining layer, with a highercontent Al at the surface away from the graded second confining layer282. The second cladding layer 284 is p-type doped with, e.g., carbon,zinc, or magnesium to a level of between 1×10¹⁷ cm⁻³ to 5×10¹⁸ cm⁻³, andhas a thickness of between 300 nm and 3000 nm, preferably 1000 nm.

The illustrated configuration forms a single mode laser with theindicated optical field distribution 285.

A p⁺ type cap layer 286 of GaAs is grown over the second cladding layer284. The cap layer 286 is doped to a level of between 5×10¹⁷ cm⁻³ to5×10²⁰ cm⁻³, and preferably about 1-3×10¹⁹ cm⁻³, and has a thickness ofbetween 10 nm and 500 nm, preferably about 300 nm thick.

A pair of spaced parallel grooves 288 (see FIG. 2 a) is formed in thecap layer 286 by photolithography and etch steps. The grooves 288 extendbetween the ends of the laser diode 200. The grooves 288 are spacedapart at a distance of about 1 μm to 10 μm and preferably about 10 μm,and extend into the second cladding layer 284 by a sufficient extent torestrict lateral transverse modes. An encapsulating layer 290 of aninsulating material, such as SiO₂ or SiN_(x) is deposited over cap layer286 and the surface of the grooves 288. The encapsulating layer 290 hasan opening 292 formed therethrough over a portion of the cap layer 286disposed between the grooves 288. A conducting top contact layer(electrode) 294, e.g., a p-type contact layer is formed over theinsulating layer 290 and extends through the opening 292 to contact thesurface of the cap layer 286. The conducting top contact layer 294 maybe formed by, e.g., deposition, sputtering, or evaporation. Theconducting top contact layer 294 includes a material that makes goodelectrical contact to the material of the cap layer 286, e.g., aTi/Pt/Au tri-layer.

In an embodiment, an electrically insulated diode (EID) structure may beadded (not shown).

After thinning the backside of the substrate by conventional waferthinning techniques, preferably to 100 μm, a conducting bottom contactlayer (electrode) 296 is formed on the bottom surface 230 of thesubstrate 100 by, e.g., deposition or evaporation. The conducting bottomcontact layer 296 is formed from a material that makes good electricalcontact to the material of the substrate 100; in a preferred embodiment,the conducting bottom contact layer 296 includes a tri-layer ofAuGe/Ni/Au with n-type conductivity.

Referring to FIG. 2 c, input and output electrical contacts (electrodes)may be also fabricated on a single side, i.e., the same side, of thesubstrate to improve electrical pumping efficiency and to reduce opticalcoupling loss at the III-V/Si interface. This can be realized bytechniques known to one of skill in the field, such as by use of anetch-stop layer (not shown) inserted between the graded first confininglayer (waveguide) 274 and graded spacer layer 272, which are disposedbetween the active region or multiple quantum well 280 and the gratinglayer 270, as shown in FIG. 2 c. For example, after the formation of thecap layer 286 and grooves 288, portions of overlying materials may beremoved by deep trench etching to expose a region of graded spacer layer272. A dielectric insulator 291 is deposited to protect a sidewallexposed by the removed portions of overlying material, as well as tocover an exposed portion of graded spacer layer 272. The dielectricinsulator 291 may include the same material and formed in the same stepas encapsulating layer 290.

A mask is defined by photolithography, and a bottom portion of thedielectric insulator 291 disposed over graded spacer layer 272 isremoved by e.g., etching, to define an opening 292′, as well as opening292 in the encapsulating layer 290.

Opening 292′ is masked by photolithographic methods, and electrode 294is deposited. Then, electrode 294 is masked and an n-contact electrode297 is defined by the formation of a thin film metal coating in opening292′ directly on top of the exposed top surface of graded spacer layer272. Thus, the electrodes 294, 297 are disposed on the same side of thesubstrate. Electrode 297 may be an output electrode and electrode 294may be an input electrode, or vice versa.

The ends of the laser diode 200 are reflective, with at least one of theends being partially transparent to allow radiation to be emitted fromthe device.

FIG. 4 is a schematic illustration of a two-section DFB laser. Structure200′ has two diffraction gratings 210 and 210′ with different gratingduty cycles based on the two different grating sections defined bydielectric layers 110, 111. Top contacts 294, 298 correspond to the twodiffraction gratings 210, 210′, respectively. When laser 200′ iselectrically pumped, one or two wavelengths λ₁, λ₂ of laser output,depending on current driving selecting, may be obtained from the samelaser facet 277 that includes the emitting surfaces of graded firstconfining layer 274, multi-quantum well region 280, and graded secondconfining layer 282. Each of the laser outputs is longitudinal singlemode.

Based on above description and techniques illustrated in FIGS. 2 a-2 cand 3, those familiar with the art can apply the concepts and maskdesign functionalities available using ART techniques to implement avariety of different multi-section DFB lasers or related optoelectronicstructures such as sensors, modulators, etc.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The foregoingembodiments are therefore to be considered in all respects illustrativerather than limiting on the invention described herein. Scope of theinvention is thus indicated by the appended claims rather than by theforegoing description, and all changes which come within the meaning andrange of equivalency of the claims are intended to be embraced therein.

1. A method of making a laser diode, the method comprising the steps of:forming a dielectric layer over a top surface of the substratecomprising a first semiconductor material; defining a plurality ofopenings in the dielectric layer, the openings extending to the topsurface of the substrate; forming a second semiconductor material in theopenings; and defining a plurality of layers over the secondsemiconductor material and the dielectric layer to form the laser diode,wherein portions of the dielectric layer define a diffraction grating.2. The method of claim 1, wherein the diffraction grating has a widthand a spacing selected to provide a duty cycle ranging from 20% to 50%.3. The method of claim 1, wherein defining the plurality of openingscomprises reactive ion etching.
 4. The method of claim 1, whereinforming the second semiconductor material comprises selective epitaxy.5. The method of claim 1, wherein the first semiconductor materialcomprises silicon and the second semiconductor material comprises atleast one of a III-V compound or a II-VI compound.
 6. The method ofclaim 1, wherein the plurality of semiconductor layers comprises atleast one of a cladding layer, a grating layer, a graded spacer layer, agraded confining layer, a quantum well region, or a cap layer.
 7. Themethod of claim 1, wherein the laser diode is a distributed feedbacklaser diode.
 8. The method of claim 1, further comprising defining abottom contact layer over a bottom surface of the substrate.
 9. Themethod of claim 1, wherein a bottom portion of the second semiconductormaterial comprises lattice-mismatch defects and a top portion of thesecond semiconductor material is substantially free of lattice-mismatchdefects.
 10. The method of claim 9, wherein each of the openings has aheight sufficient for trapping a majority of the lattice-mismatchdefects within the opening.
 11. The method of claim 1, wherein each ofthe plurality of openings has a width less than or equal to a heightthereof.
 12. A semiconductor device comprising: a plurality of openingsdefined in a dielectric layer disposed above a crystalline substratecomprising a first semiconductor material; a diffraction grating definedby portions of the dielectric layer disposed between the openings; asecond crystalline material disposed within each of the openings, thesecond crystalline material having a lattice mismatch with thesubstrate, and a majority of defects arising from lattice mismatchbetween the second material and the substrate exiting at a surface ofthe second material within each of the openings; and a plurality ofsemiconductor layers disposed above the second crystalline material andthe diffraction grating, the plurality of semiconductor layers forming alaser diode.
 13. The device of claim 12 wherein the first semiconductormaterial comprises silicon.
 14. The device of claim 12 wherein thesecond crystalline material comprises at least one of a III-V compoundor a II-VI compound.
 15. The device of claim 12 wherein the diffractiongrating provides a duty cycle ranging from 20% to 50%.
 16. The device ofclaim 12 wherein the laser diode is a distributed feedback laser.
 17. Adistributed feedback laser device comprising: a dielectric diffractiongrating disposed over a crystalline substrate; and a plurality of layersdisposed above the diffraction grating, wherein the layers define alaser diode, and at least some of the layers comprise a III-V materiallattice-mismatched to the crystalline substrate.
 18. The device of claim17 wherein the diffraction grating comprises a dielectric layer defininga plurality of openings.
 19. The device of claim 18, further comprisinga crystalline material disposed within the openings, the crystallinematerial having a lattice constant mismatched to a lattice constant ofthe crystalline substrate.
 20. The device of claim 19, furthercomprising a contact disposed on a bottom side of the crystallinesubstrate.
 21. The device of claim 19, further comprising an inputelectrode and an output electrode disposed on a single side of thecrystalline substrate.
 22. The device of claim 19, wherein a top portionof the crystalline material is substantially free of defects.
 23. Thedevice of claim 17, wherein the crystalline substrate comprises a groupIV material.
 24. A method of making a laser diode, the method comprisingthe steps of: forming a dielectric layer over a crystalline substratecomprising a first semiconductor material; forming a first diffractiongrating by: defining a first plurality of openings in the dielectriclayer above a top surface of the crystalline substrate, the firstdiffraction grating generating a first output wavelength; forming asecond diffraction grating by: defining a second plurality of openingsin the dielectric layer above the top surface of the crystallinesubstrate, the second diffraction grating generating a second outputwavelength; and defining a plurality of layers over the first and seconddiffraction gratings to form the laser diode.
 25. A distributed feedbacklaser device comprising: a dielectric layer disposed over a crystallinesubstrate comprising a first semiconductor material; a first diffractiongrating defined by a first plurality of openings in the dielectric layerabove a top surface of the crystalline substrate, the first diffractiongrating generating a first output wavelength; a second diffractiongrating defined by a second plurality of openings in the dielectriclayer above the top surface of the crystalline substrate, the seconddiffraction grating generating a second output wavelength; and aplurality of layers disposed over the first and second diffractiongratings defining a distributed feedback laser device active region.